The present invention is directed to improvements in the termination region of vertical, insulated-gate-controlled devices, such as Insulated Gate Bipolar Transistors (IGBTs), Insulated Gate Turn-off Devices (IGTOs), and other related devices that switch between an on state and an off state to control power to a load, such as a motor. Such devices may conduct many amps and have a breakdown voltage in excess of 500 volts. An example of a prior art IGTO is shown in FIG. 1 to illustrate the problem with high current densities being created in the termination region surrounding the cellular array. The details of the device's operation are not important but are presented below for completeness.
Prior art FIG. 1 is a cross-section of a small portion of an IGTO device 10 (similar in some respects to a thyristor) reproduced from the assignee's U.S. Pat. No. 8,878,237, incorporated herein by reference. The portion is near an edge of the device and shows a plurality of cells having vertical gates 12 (e.g., doped polysilicon) formed in insulated trenches. A 2-dimensional array of the cells may be formed in a common p-well 14, and the cells are connected in parallel. The area containing the cells is shown as the active region 15. The edge of the device suffers from field crowding, and the edge cell is modified to increase ruggedness of the device. The edge cell has an opening 16 in the n+ source region 18 where the cathode electrode 20 shorts the n+ source region 18 to the p-well 14. Such shorting increases the tolerance to transients to prevent unwanted turn on and prevents the formation of hot spots. The configuration of the edge cell may also be used in other cells of the device for a more uniform current flow across the device.
The vertical gates 12 are insulated from the p-well 14 by an oxide layer 22. A p+ contact (not shown) may be used at the opening 16 of the edge cell for improved electric contact to the p-well 14. The narrow gates 12 are connected together outside the plane of the drawing and are coupled to a gate voltage via the gate electrode 25 contacting the polysilicon portion 28. A patterned dielectric layer 26 insulates the metal from the various regions. The field limiting rings 29 at the edge of the cell in the termination region 27 reduce field crowding for increasing the breakdown voltage. The termination region 27 is designed to break down at a voltage higher than the breakdown voltage of the active region 15, since the cathode electrode 20 is over the active region 15 and can efficiently conduct the breakdown current. The termination region 27 surrounds the active region 15, which may have a generally rectangular shape. The active region 15 may take up the center area of a die or may be formed in strips separated by termination regions 27.
An NPNP semiconductor layered structure is formed in FIG. 1. There is a bipolar PNP transistor formed by a p+ substrate 30, an n-epitaxial (epi) layer 32, and the p-well 14. There is also a bipolar NPN transistor formed by the n-epi layer 32, the p-well 14, and the n+ source region 18. An n-type buffer layer 35, which may be epitaxially grown or formed by implantation into the substrate 30, has a dopant concentration higher than that of the n-epi layer 32. The buffer layer 35 helps to set the breakdown voltage and reduces hole injection into the n-epi layer 32. A metal, bottom anode electrode 36 contacts the substrate 30, and a metal, cathode electrode 20 contacts the n+ source region 18. The p-well 14 surrounds the gate structure, and the n-epi layer 32 extends to the surface around the p-well 14.
When the anode electrode 36 is forward biased with respect to the cathode electrode 20, but without a sufficiently positive gate bias, there is no current flow, since the product of the betas (gains) of the PNP and NPN transistors is less than one (i.e., there is no regeneration activity).
When the gate is forward biased, electrons from the n+ source region 18 become the majority carriers along the gate sidewalls in an inversion layer, referred to as a “voltage induced emitter,” causing the effective width of the NPN base (the portion of the p-well 14 between the n-layers) to be reduced. As a result, the beta of the NPN transistor increases to cause the product of the betas to exceed one. This condition results in device turn-on, with holes being injected into the lightly doped n-epi layer 32 and electrons being injected into the p-well 14. Accordingly, the gate bias initiates the turn-on, and the full turn-on (due to regenerative action) occurs when there is current flow through both the NPN transistor and the PNP transistor.
When the gate bias is removed, such as the gate electrode 25 being shorted to the cathode electrode 20, the IGTO device turns off.
Applicants have discovered that, as a result of the heavily doped p+ substrate 30 below the termination region 27, there is a relatively high injection of carriers (holes) from the substrate 30 into the n-epi layer 32 (base) when the IGTO device 10 is on. When the IGBT 10 is turned from on to off, the injected carriers in the termination region 27 can result in device failure due to the high heat created when removing the excess carriers, resulting in thermal destruction in the termination region 27. This problem limits the acceptable maximum current that can be conducted in the on-state.
This general cause of device destruction due to high carrier injection into a termination region is described in the paper, “LPT(II)-CSTBT™(III) for High Voltage Application with Ultra Robust Turn-Off Capability Utilizing Novel Edge Termination Design,” by Ze Chen et al., Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, 3-7 Jun. 2012, incorporated herein by reference. That paper describes a high voltage IGBT using an n-type substrate. All the devices in the active region are formed by doping from the top surface of the n-type substrate. The bottom p-type layer (anode) is formed by doping the bottom surface of the n-type substrate. The bottom p-type layer is formed by masking the bottom surface of the n-type substrate during implantation so that the p-type layer is heavily doped below the active region and only lightly doped below the termination region. This light doping below the termination region reduces the injected carriers (holes) in the termination region during the on-state, so that when the IGBT is turned off, there is much less heating effect from the injected carriers in the termination region.
However, such a prior art technique does not suggest how to achieve similar results in vertical gate-controlled devices where the active cell array is not formed directly in the top surface of an n-type substrate, but is formed in an n-type epitaxial layer grown over a p+ substrate. It is not feasible to dope the bottom surface of a p+ substrate to obtain different doping levels at the top surface of the substrate, where the n-type epitaxial layers are grown over the top surface of the substrate. Other problems exist when using a starting p+ substrate.
Therefore, what is needed are techniques for reducing carrier injection into the termination region of a vertical, insulated-gate device, where the active region is formed in an epitaxial layer of a first conductivity type (e.g., n-type) over a growth substrate of a second conductivity type (e.g., p-type).